With the growing trend for a high resolution, high performance liquid crystal display device, liquid crystal drivers (IC chips) incorporated in the liquid crystal display device need to provide increasing numbers of outputs.
Typical IC chips satisfy this demand by reducing chip size or narrowing pitches for bumps on the chip. COF (chip on film) technology is recently popular whereby bare chip liquid crystal drivers which enable fine pitches are mounted.
Latest COF packaging applies heat and pressure in electrically connecting a tape carrier to an IC chip to couple the bumps on the IC chip to the inner leads on the tape carrier. To eliminate discrepancies in position between the bumps and the inner leads, the coupling method needs to utilize carrier tape material that hardly deforms under heat and enables high resolution. In other words, as finer pitches are pursued, more constraints are placed on choices for the tape carrier material.
This drawback is addressed, for example, by patent literature 1 which discloses a method of connecting an IC chip to a circuit board (tape carrier) via an interposer. FIG. 13 is a cross-sectional view of the package structure taken from patent literature 1.
As illustrated in FIG. 13, an IC chip 104 is flip-chip connected to the interposer 101. The interposer 101 is in turn connected by bumps to an electrode pattern 110 on a circuit board 107. The interposer 101 is a silicon (Si) substrate and produced by a Si wafer process so that the electrodes to which the IC chip 104 is connected have fine pitches equivalent to those of the electrodes on the IC chip 104. In contrast, the electrodes to which the circuit board 107 is connected are formed to match the relatively wide electrode pitches of the circuit board 107. The electrodes to which the IC chip 104 is connected are connected to the respective electrodes to which the circuit board 107 is connected on the interposer 101. The circuit board 107 may be a tape carrier.
The provision of the intervening interposer 101 enables redistribution of the fine pitches achieved in IC processes for the electrode pitches on the tape carrier. Applying this technique to the COF package allows relaxing the constraints on choices for the tape carrier base material even when the IC chip has extremely fine pitched electrodes as a result of the reduced size or increased number of outputs of the IC chip.
To provide the fine pitches, the IC chip 104 is connected to the interposer 101 by metal or alloy bumps that are relatively hard and have a high melting point (e.g., Au—Au joints by means of Au bumps). The use of such material resolves problems of short-circuiting between adjacent bumps by reducing bump deformation, which in turn allows for reduction in terminal pitch to about 25 μm and provision of large numbers of IC chip outputs.
Meanwhile, the interposer is connected to the tape carrier through terminals with greater pitches than the IC chip contacts, for example, with 50 to 100 μm pitches.
If the circuit board 107 is made of such a thin material, like a tape carrier or a film carrier, that one can see through the circuit board 107, the circuit board 107 and the interposer 101 can be aligned in attaching the circuit board 107 and the interposer 101 in the manufacture of the package while observing them on a face of the circuit board 107 opposite the interposer 101. This method cannot be used in aligning the interposer 101 and the IC chip 104 in attaching the interposer 101 and the IC chip 104 because the interposer 101 is made of, for example, silicon and too thick to see through and one cannot see through the IC chip 104 either.
Some IC chips have an exterior partially deformed out of design dimensions in dicing due to some reasons in manufacturing equipment although the deformation may not affect their performance. The interposer may be provided with marks designed to enable aligning to the exterior of the IC chip. However, since the marks are made according to the IC chip with as-designed dimensions, they do not enable accurate aligning in the packaging of a deformed IC chip.
Accordingly, patent literature 2 discloses aligning two substrates using alignment marks shown in FIG. 14. FIG. 14 is a schematic illustration of the shape of alignment marks and a method of aligning using the alignment marks in accordance with an embodiment of the present invention. In the figure, (a) is plan views of the two substrates, (b) is cross-sectional views along line A-A′ and line B-B′ of the substrates, and (c) is a drawing illustrating the substrates, one being placed on top of the other. As can be seen from FIG. 14, a first silicon substrate S1, which has a (100) plane, is provided with two rectangular alignment grooves 201a and 201a as alignment marks 201 running in the <110> direction. A second silicon substrate S2, which has a (100) plane, is similarly provided with two rectangular alignment grooves 202a and 202a as alignment marks 202 separated by a distance and running parallel in the <110> direction. The alignment grooves 202a and 202a on the second substrate S2 exactly match the alignment grooves 201a and 201a on the first silicon substrate S1 if rotated by 90°. Patent literature 2 describes that the alignment grooves are observed with the first substrate S1 being attached to the second substrate S2, by means of infrared, X-ray, or like transmitted light. With the first substrate S1 being correctly aligned to the second substrate S2, an overlapping pattern of the two marks 201 and 202 are observed as illustrated in (c) of FIG. 14.